module PC(CLK,newaddr, addr, reset, block);

   input CLK;
   input block;
   input [31:0] newaddr;
	input reset;
   output [31:0] addr;
   reg [31:0]    PC;

   assign addr = PC;

   always @(posedge CLK or posedge reset)
     begin
        if (reset) begin
           PC <= 0;
        end else if (block) begin
        end else begin
	         PC <= newaddr;
        end
     end

endmodule
